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extract_fa: Fix xor3/xnor3 inversion bug #4691

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extract_fa: Fix xor3/xnor3 inversion bug #4691

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d8863e4
extract_fa: Add test case
jix Oct 30, 2024
64d298e
extract_fa: Invert xor3/xnor3 output when inverting majority3 input
hovind Oct 30, 2024
84d0c8f
extract_fa: Simplify xor2/xnor2 negation
hovind Oct 30, 2024
9421558
extract_fa: Remove redundant code
hovind Oct 30, 2024
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17 changes: 6 additions & 11 deletions passes/techmap/extract_fa.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -344,13 +344,6 @@ struct ExtractFaWorker
if (func3.at(key).count(func) == 0)
continue;

if (func3.at(key).count(xor3_func) == 0 && func3.at(key).count(xnor3_func) != 0) {
f3i.inv_a = !f3i.inv_a;
f3i.inv_b = !f3i.inv_b;
f3i.inv_c = !f3i.inv_c;
f3i.inv_y = !f3i.inv_y;
}

if (!f3i.inv_a && !f3i.inv_b && !f3i.inv_c && !f3i.inv_y) {
log(" Majority without inversions:\n");
} else {
Expand Down Expand Up @@ -412,14 +405,15 @@ struct ExtractFaWorker
facache[fakey] = make_tuple(X, Y, cell);
}

bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c;
if (func3.at(key).count(xor3_func)) {
SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
for (auto bit : func3.at(key).at(xor3_func))
assign_new_driver(bit, YY);
}

if (func3.at(key).count(xnor3_func)) {
SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
for (auto bit : func3.at(key).at(xnor3_func))
assign_new_driver(bit, YY);
}
Expand Down Expand Up @@ -516,14 +510,15 @@ struct ExtractFaWorker
cell->setPort(ID::Y, Y);
}

auto invert_y = f2i.inv_a ^ f2i.inv_b;
if (func2.at(key).count(xor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y;
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
for (auto bit : func2.at(key).at(xor2_func))
assign_new_driver(bit, YY);
}

if (func2.at(key).count(xnor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y);
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
for (auto bit : func2.at(key).at(xnor2_func))
assign_new_driver(bit, YY);
}
Expand Down
29 changes: 29 additions & 0 deletions tests/various/bug3879.ys
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Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
read_verilog <<EOF
module gcd(I, D);

output [2:0] I;
input [3:0] D;

assign I = D[0]+D[1]+D[2]+D[3];
endmodule
EOF
design -save input

prep

design -stash gold

design -load input

synth -top gcd -flatten

extract_fa -v

design -stash gate

design -copy-from gold -as gold gcd
design -copy-from gate -as gate gcd

miter -equiv -make_assert -flatten gold gate miter

sat -verify -prove-asserts -show-all miter