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@YosysHQ

Yosys Headquarters

Yosys Open SYnthesis Suite

YosysHQ - Open Source EDA

OSS CAD Suite: the one-stop shop for our tools

If you want to use our EDA tools, the easiest way is to install the binary release OSS CAD suite, which contains all required dependencies and related tools. Find the documentation here. We also have an OSS CAD Suite github action for using the tools in a github CI workflow.

Tabby CAD Suite is a commercial extension of OSS CAD Suite available from YosysHQ GmbH that additionally includes the Verific frontend for industry-grade SystemVerilog and VHDL support, formal verification with SVA, and formal apps.

Our Projects

Front-ends for applications built on top of Yosys:

  • sby: formal property checking
  • mcy: mutation coverage
  • eqy: equivalence checking

Other notable projects:

  • riscv-formal: formally check compliance with the RISC-V specification
  • picorv32: A Size-Optimized RISC-V CPU
  • nerv: A very simple educational RISC-V CPU for demonstrating riscv-formal

Community

Support us

Like what we do? Please consider either buying a license for the Tabby CAD Suite or becoming a sponsor.

Pinned Loading

  1. yosys yosys Public

    Yosys Open SYnthesis Suite

    C++ 3.5k 888

  2. nextpnr nextpnr Public

    nextpnr portable FPGA place and route tool

    C++ 1.3k 243

  3. sby sby Public

    SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

    Python 403 75

  4. oss-cad-suite-build oss-cad-suite-build Public

    Multi-platform nightly builds of open source digital design and verification tools

    Shell 837 75

Repositories

Showing 10 of 38 repositories
  • oss-cad-suite-build Public

    Multi-platform nightly builds of open source digital design and verification tools

    YosysHQ/oss-cad-suite-build’s past year of commit activity
    Shell 837 ISC 75 46 1 Updated Nov 1, 2024
  • imctk Public

    Incremental Model Checking Toolkit

    YosysHQ/imctk’s past year of commit activity
    Rust 2 2 9 1 Updated Oct 31, 2024
  • yosys Public

    Yosys Open SYnthesis Suite

    YosysHQ/yosys’s past year of commit activity
    C++ 3,473 ISC 888 451 121 Updated Oct 30, 2024
  • eqy Public

    Equivalence checking with Yosys

    YosysHQ/eqy’s past year of commit activity
    Python 30 5 9 0 Updated Oct 29, 2024
  • apicula Public

    Project Apicula 🐝: bitstream documentation for Gowin FPGAs

    YosysHQ/apicula’s past year of commit activity
    Verilog 487 MIT 67 13 4 Updated Oct 24, 2024
  • nextpnr Public

    nextpnr portable FPGA place and route tool

    YosysHQ/nextpnr’s past year of commit activity
  • sby Public

    SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

    YosysHQ/sby’s past year of commit activity
    Python 403 75 41 11 Updated Oct 17, 2024
  • riscv-formal Public

    RISC-V Formal Verification Framework

    YosysHQ/riscv-formal’s past year of commit activity
    Verilog 103 ISC 24 3 3 Updated Oct 16, 2024
  • nerv Public

    Naive Educational RISC V processor

    YosysHQ/nerv’s past year of commit activity
    SystemVerilog 71 12 1 2 Updated Oct 13, 2024
  • mcy Public

    Mutation Cover with Yosys (MCY)

    YosysHQ/mcy’s past year of commit activity
    C++ 77 ISC 9 1 0 Updated Oct 9, 2024

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