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41 Open 94 Closed
41 Open 94 Closed
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Issues list

ERROR: Assert `formal' failed in passes/memory/memory_map.cc:234
#307 opened Oct 31, 2024 by CrazybinaryLi
Not able to identify which assertion failed when using generators
#306 opened Oct 29, 2024 by zputrle
1
Generated test banches cannot be used with Xcelium or Iverilog
#300 opened Oct 11, 2024 by zputrle
Handle inout ports automatically and produce errors if not possible
#299 opened Oct 1, 2024 by jix
1
X/Z bits in property mishandled by btor backend
#295 opened Aug 23, 2024 by nakengelhardt
Pycode
#291 opened Jul 25, 2024 by AdamKeith1
Local sva variables assignment is resulting in error.
#285 opened Jul 22, 2024 by Humblefool14
Previously working example now fails on newest version
#279 opened Jun 2, 2024 by fayalalebrun
3
Error regarding std::bad_alloc
#265 opened Mar 7, 2024 by natureangel
1
Yosys doesn't work on btor pono engine.
#257 opened Dec 20, 2023 by CrazybinaryLi
1
Unexpected behaviour with asynchronous reset
#255 opened Dec 4, 2023 by mpardalos
8
sby depends on click without specifying a version constraint
#234 opened Feb 27, 2023 by whitequark
4
VCD dump for PASS
#233 opened Feb 20, 2023 by marvintau
1
[RFC] Ensuring code is formatted in accordance to pep8
#208 opened Aug 4, 2022 by lethalbit
2
Yices 2 default solver despite being 'optional'
#165 opened May 30, 2022 by KrystalDelusion
3
Absolute paths in Windows discuss to be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/)
#162 opened May 30, 2022 by KrystalDelusion
tests require super_prove, which requires python-pip, which isn't available on ubuntu 20.04
#160 opened May 25, 2022 by programmerjake
5
SV RTL support for local for loops
#118 opened Nov 13, 2020 by lighteningfingers
Support for SVA Local Variables
#114 opened Sep 8, 2020 by dh73
1
Incorrectly instantiated DUT ports in the auto generated testbench when using SystemVerilog interface
#113 opened Sep 4, 2020 by dh73
1
SymbiYosys doesn't handle latches properly
#111 opened Aug 25, 2020 by ZipCPU
1
BMC fails while induction proof succeeds bug
#103 opened Jul 22, 2020 by kentindell
1
vcd file includes blank traces
#91 opened Jun 12, 2020 by mattvenn
7
Generated trace files dump bit vectors for enum signals
#83 opened Apr 12, 2020 by tudortimi
Can't set value of enum parameter using 'chparam'
#82 opened Apr 12, 2020 by tudortimi
2
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