opt_lut_ins doesn't do anything here, they can be removed.

opt_lut_ins doesn't do anything here, they can be removed.

Thank you for your reply! I have removed the opt_lut_ins pass, but the issue still persists. The current pass sequence is:hierarchy; proc; opt_clean; opt_dff; opt_demorgan; opt_merge; opt_reduce; opt_dff; opt_expr; opt_muxtree; opt_share; opt_dff; opt_clean; opt_reduce; opt_demorgan;

read_ilang <<EOT
autoidx 1
module \top
  wire output 1 \Y
  cell $reduce_or $reduce_or$rtl.v:29$20
    parameter \A_SIGNED 0
    parameter \A_WIDTH 0
    parameter \Y_WIDTH 1
    connect \A { }
    connect \Y \Y
  end
end
EOT

opt_demorgan

Looks like an issue where A_WIDTH is 0. For what its worth opt_demorgan is an old pass that doesn't really get used anywhere (its not called in other opt scripts, only if you invoke it manually)

read_ilang <<EOT
autoidx 1
module \top
  wire output 1 \Y
  cell $reduce_or $reduce_or$rtl.v:29$20
    parameter \A_SIGNED 0
    parameter \A_WIDTH 0
    parameter \Y_WIDTH 1
    connect \A { }
    connect \Y \Y
  end
end
EOT

opt_demorgan

Looks like an issue where A_WIDTH is 0. For what its worth opt_demorgan is an old pass that doesn't really get used anywhere (its not called in other opt scripts, only if you invoke it manually)

Thank you for your help.

The other part of this is that the rtlil contains zero width cells now, which isn't particularly nice. In this case this is happening because opt_reduce is being called on |4'b0000. It would probably be good to special case this in opt_reduce to produce constant 1/0 for these cases