Add IS43LQ32256A-062BLI and alias IS43LQ32256AL-062BLI.

[mhrdmhrd]

Added IS43LQ32256A-062BLI (LPDDR4 SDRAM) and alias IS43LQ32256AL-062BLI (LPDDR4X SDRAM).
Both of the two components shared the same symbol, footprint, and package dimensions. Only the difference is the voltage of VDDQ.

Datesheet: http://www.issi.com/WW/pdf/43-46LQ32256A-AL.pdf

Unit A contains function pins of channel A:

Unit B contains function pins of channel B:

Unit C mainly contains power, ground, an DNU (do not use) pins of channel A:

Unit D mainly contains power, ground, an DNU (do not use) pins of channel B:

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In preparation for the KiCad v6 release this repository will be locked down on Sept 1, 2020. No new pull requests will be accepted. Existing pull requests can be worked on until Oct 1, 2020. Changes breaking v5.1 compatibility can be merged starting Sept 1, 2020.

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We plan to convert the library to the new v6 S-expr format after it is imported to GitLab. That also means that old pull requests will need to be redone with the v6 format if they are not merged before then.

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All contributions to the kicad library must follow the KiCad library convention

Thanks for creating a pull request to contribute to the KiCad libraries! To speed up integration of your PR, please check the following items:

• Provide a URL to a datasheet for the symbol(s) you are contributing
• Provide a screenshot of the symbol(s) from the symbol editor with the pin types visible
• Ensure that the associated footprints match the official footprint library
  • A new fitting footprint must be submitted if the library does not yet contain one.
• If there are matching footprint PRs, provide link(s) as appropriate
  Footprint PR: Added BGA-200 pitch 0.80x0.65 mm for LPDDR4/4X SDRAM. kicad-footprints#2437
  3D model PR: Added 3D model for IS43LQ32256A-062BLI. kicad-packages3D#723
• Check the output of the Travis automated check scripts - fix any errors as required
• Give a reason behind any intentional library convention rule violation.
  It has S4.2 violation. I put power and ground pins separate unit C and D because the devices have too many power and ground pins. If I obeyed the rule, the width of unit A and B become too wide. It makes the schematic a bit ugly.

Note 1: Some NC pins are next to function pins like CS, CKE, ZQ because future products may use the NCs as the 2nd and 3rd one each. The pin arrangement will make easier to enhance the variation of LPDDR4/4X symbol library.
(The international standard of LPDDR4/4X defines up to three pairs of CS/CKE/ZQ.)

Note 2: Why I put DNU pins on Unit C and D was that some LPDDR4/4X vendors allow the pins to connect VSS, so it might be convenient to be there. ISSI does not support such usage, but it can be useful if someone reuse this symbol for other vendors' devices.

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Be patient, we maintainers are volunteers with limited time and need to check your contribution against the datasheet. You can speed up the process by providing all the necessary information (see above). And you can speed up the process even more by providing additional info like the screenshot of the symbol editor pin table (or for high pin counts converted to csv) sorted in the same way as the pin table in the datasheet and a direct link to the datasheet page that contains the pin table.

[CLAassistant]

All committers have signed the CLA.

[mhrdmhrd]

Thank you for reviewing my PR.
There is S4.2 violation because I put power and ground pins on separate units C and D because the device has too many power and ground pins. If I obeyed the rule, the width of unit A and B become too wide. It makes schematics a bit ugly.

[myfreescalewebpage]

Hello @mhrdmhrd thanks for this contribution

Partial review:

• Pin length should be 200mil for this symbol (4 characters for pin name, 50mil per character)
• You should stack VSS together, and VDD1 together and VDD2 together and VDDQ together. You can do it on a separated unit which will be very small. Moreover Positive power pin should go to the top, and negative to the bottom
• NC pins go on the border outline of the symbol
• Size of the unit 1 and unit B can be reduce, you have plenty of space lost at the top and the bottom

Joel

[mhrdmhrd]

Hello Joel,

Thank you for taking time to review my PR.
I have corrected this symbol. Unit C and D are removed because stacking power pins reduced area so the pins could move to unit A and B.

• Pin length should be 200mil for this symbol (4 characters for pin name, 50mil per character)
• You should stack VSS together, and VDD1 together and VDD2 together and VDDQ together. You can do it on a separated unit which will be very small. Moreover Positive power pin should go to the top, and negative to the bottom
• NC pins go on the border outline of the symbol
• Size of the unit 1 and unit B can be reduce, you have plenty of space lost at the top and the bottom

Unit A:

Unit B:

Thank you!
Minori

[myfreescalewebpage]

Thanks, great job! Continue the review now:

• Package at the end of the descriptions should be "BGA-200"
• Name of H4 is "CS0_A" and name of R4 is "CS0_B"
• P4 is CKE0_B and P5 is NC (you have cross the pins!)

Joel

[mhrdmhrd]

Thank you for your checking.
I have corrected the mistakes and checked if the all pin numbers and names corresponding the definitions in the datasheet again.

• Package at the end of the descriptions should be "BGA-200"
• Name of H4 is "CS0_A" and name of R4 is "CS0_B"
• P4 is CKE0_B and P5 is NC (you have cross the pins!)

Unit A:

Unit B:

Thank you!
Minori

[myfreescalewebpage]

BGA-200 in the description of the alias too please ;)

[mhrdmhrd]

I have also corrected the alias. Sorry for the mistake.
I completely forgot that aliases have the different description...

[myfreescalewebpage]

No problem, thanks for the update. Just need to wait the footprint now.

[mhrdmhrd]

Just let you know that the footprint PR has been merged.
I'm not in a rush. When you get some time, can you merge this PR.

[myfreescalewebpage]

Sure :)

[myfreescalewebpage]

Closing/opening to refresh the Travis test.

[myfreescalewebpage]

Thanks, no more comment, merging.

[mhrdmhrd]

Thank you so much for your time and all the effort!