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RISE RP005 QEMU weekly report 2024-10-16

Version 3 of the patches is upstream, version 4 is following shortly to address the latest feedback. Drafted a timeline for the new agreed set of goals.

We'll skip the next meeting as most of the Embecosm team will be at the RISC-V Summit and the LLVM Developers Meeting.

Work completed since last report

  • WP2

    • Measure impact of 8 bytes per iteration patch:
    • Single instruction benchmarking relevant to SiFive library functions:
    • Continue to work on AArch64 comparison:
    • Work on new optimizations for vector loads/stores.
      • Identify optimizations for those of the 14 SiFve string/memory functions where the current patch shows no improvement.

  • Paused to follow new priorities

    • Measure the glibc bencmark with VLEN=128/LMUL=1 Stopped to follow new priorities
    • Drafted a timeline for the new tasks (see below).
    • Added a new version of the patches to address endianness and atomicity issues.
      • extra feedback received, a new version in progress.

  • Actions:

    • Max: run SPECCPU 2017 results again with VLEN=128 and LMUL=1. Complete

Work plan for the coming months

  1. Ashling/Embecosm to ensure that the SiFive memory/string benchmarks are running in the shared repository at https://github.com/embecosm/rise-rvv-tcg-qemu-tooling
  • estimated completion by the end of October
  1. Ashling/Embecosm to complete the upstreaming of the two patches that Paolo has posted upstream, including resolution of all maintainer feedback. Our understanding is that this involves addressing existing feedback about endianness issues with the patches but would also include any subsequent upstream maintainer requests.
  • estimated completion by the end of October

New optimizations

  1. Optimization of whole register vector loads/stores through tcg generation.
  2. Optimization of fault-only-first loads emulation loops.
  3. Optimization of strided/indexed loads/stores by elimination of redundant operations.
  • estimated completion time: end of November.
  • estimated upstreaming completion time (in the limits of our control) mid December.

Work planned for the coming week

  • WP2

    • Upstream fixes for the latest feedback.
    • Start optimization for whole register load/store operations through tcg op generation.
    • Investigate the SIGILL QEMU error in the SiFive library functions

  • Actions:

    • Paolo to update the slides for the RISC-V Summit.
    • Nathan/Paolo to reproduce the SIGILL QEMU error in the SiFive library functions.

Planned absences

  • Jeremy Bennett will be on vacation 12-19 October
  • Jeremy Bennett will be at the RISC-V NA Summit 21-24 October
  • Paolo Savini will be at the LLVM Developers' Meeting 22-24 October
  • Paolo Savini will be on vacation 8 November and 13-18 November